1. Field of the Invention
The present general inventive concept relates to semiconductor fabrication apparatuses and methods of forming a semiconductor device using the same, and more particularly, to semiconductor fabrication apparatuses to perform semiconductor etching and deposition processes and methods of forming the semiconductor device using the same.
2. Description of the Related Art
Typically, semiconductor devices are fabricated using a semiconductor substrate and a material layer. Here, the semiconductor devices may be configured to correspond to predetermined regions of the semiconductor substrate, respectively, thereby having electrical characteristics corresponding to the material layer. The material layer may be formed by performing a semiconductor deposition process on the semiconductor substrate. The predetermined region of the semiconductor substrate may be formed by performing a semiconductor photolithography process on the semiconductor substrate. After performing of the semiconductor photolithography and deposition processes, the semiconductor substrate may be exposed to a semiconductor etching process together with the material layer to form semiconductor devices.
However, the semiconductor etching process may be performed to expose a main surface of the semiconductor substrate through a material layer, and form residues of the material layer in a bevel region of the semiconductor substrate. The residues of the material layer are different in number depending on characteristics of the semiconductor etching process and formed in the bevel region of the semiconductor substrate. The residues of the material layer may be transferred from the bevel region of the semiconductor substrate to the main surface of the semiconductor substrate to electrically short-circuit semiconductor devices through the semiconductor etching process or subsequent semiconductor fabrication processes after performing the semiconductor etching process.
A method of preventing occurrence of residues of an insulating layer (corresponding to a material layer) in a bevel region of the semiconductor substrate is disclosed in Japanese Patent Laid-open Publication No. 2002-334879, filed by Fukata Shinichi et al. According to Japanese Patent Laid-open Publication No. 2002-334879, an insulating layer covering a peripheral region and a bevel region of a semiconductor substrate is formed. A passivation layer is formed in the bevel region of the semiconductor substrate to be disposed on the insulating layer. An interconnection groove is formed in the insulating layer by performing a semiconductor etching process on the insulating layer to expose the semiconductor substrate. The passivation layer protects the insulating layer in the bevel region of the semiconductor substrate during the etching process and prevents occurrence of the residues of the insulating layer in the bevel region of the semiconductor substrate.
However, the method disclosed in Japanese Patent Laid open Publication No. 2002-334879 includes performing a semiconductor deposition process twice in different places of a semiconductor fabrication line not to make residues of the insulating layer in the bevel region of the semiconductor substrate. The two-time semiconductor deposition processes are performed using techniques of chemical vapor deposition (CVD) and organic material coating. Thus, the semiconductor substrate has to be moved to semiconductor fabrication apparatuses disposed in different places to perform the semiconductor deposition process twice. Thus, the method according to Japanese Patent Laid-open Publication No. 2002-334879 may prolong a processing time for forming the interconnection groove relating to the residues of the insulating layer, thereby increasing production cost of the semiconductor device.